1. Field of the Invention
Embodiments of the present invention generally relate to a thin film transistor (TFT) fabrication method.
2. Description of the Related Art
Current interest in TFT arrays is particularly high because these devices may be used in liquid crystal active matrix displays (LCDs) of the kind often employed for computer and television flat panels. The LCDs may also contain light emitting diodes (LEDs) for back lighting. Further, organic light emitting diodes (OLEDs) have been used for active matrix displays, and these OLEDs utilize TFTs for addressing the activity of the displays.
TFTs made with amorphous silicon as the active material have become the key components of the flat panel display industry. There are two general types of TFTs in industry. The first type is called a top gate TFT because the gate electrode is located above the source and drain electrodes. The second type is called a bottom gate TFT because the gate electrode is located below the source and drain electrodes. In the bottom gate TFT structure, the source and drain electrodes are disposed over the active material layer.
The source and drain electrodes in a bottom gate TFT may be fabricated by depositing a metal layer over the active material layer and then etching the metal layer to define the source and drain electrodes. During the etching, the active material layer may be exposed to etch chemistry. Often, metal oxide or oxynitride semiconductors have less resistance to wet chemistry but have high resistance to plasma dry chemistry compared to the source-drain metals. Therefore, it is a challenge to etch source-drain metal electrodes using wet chemistry without significantly damage to the semiconductor channel layer. Thus, dry etch of the source-drain metal is often preferred. However, not all metals can be etched effectively through dry plasma etch, for example, copper. To prevent exposure of the active material layer to the undesired dry or wet etch chemistry, an etch stop or a dual metal layer may be used.
An etch stop bottom gate TFT has an etch stop layer deposited between the active material layer and the metal layer used for the source and drain electrodes. The etch stop layer is blanket deposited and then etched using a mask such that the remaining portion of the etch stop is disposed over the gate electrode. Thereafter, the metal layer is blanket deposited followed by etching the active material layer and the metal layer with a mask. Then, the source and drain electrodes are defined by etching through the metal layer using a mask. Thus, the etch stop bottom gate TFT utilizes at least five masks for the patterning (i.e., to pattern the gate electrode, to pattern the etch stop, to pattern the active material layer and metal layer, to expose the active material layer and form the active channel, and to define the source and drain electrodes). If a cross-dielectric contact is formed, then an additional mask may be used. The bottom gate TFTs without etch stops, by contrast, necessitate at least one less mask which therefore has made the bottom gate TFTs without etch stops the preferred TFT despite the better performance of the etch stop bottom gate TFTs.
In the multi-metal layer structure, the top metal can be etched with almost any dry or wet etch chemistry. The metal layer close to active channel layer is selected so that it will not be completely etched during the etching of the top metals, and it can be easily etched under certain process condition without harming the active layer. For example Cu can be selected as the top metal and Mo can be selected as the metal contacting the semiconductor.
Therefore, there is a need in the art for an etch stop bottom gate TFT fabrication method using wet metal etching chemistry that utilizes fewer masks.